Samsung Tapes Out Its First 3nm Smartphone SoC, Will get A Improve From Synopsys AI-Enabled Devices

This week Samsung Electronics and Synopsys launched that Samsung has taped out its first cell system-on-chip on Samsung Foundry’s 3nm gate-all-around (GAA) course of experience. The announcement, coming from digital design automation Synopsys, further notes that Samsung used the Synopsys.ai EDA suite to place-n-route the format and ensure design of the SoC, which in flip enabled larger effectivity.

Samsung’s unnamed high-performance cell SoC is dependent upon ‘flagship’ general-purpose CPU and GPU architectures along with various IP blocks from Synopsys. SoC designers used Synopsys.ai EDA software program program, along with the Synopsys DSO.ai to fine-tune design and maximize yields along with Synopsys Fusion Compiler RTL-to-GDSII decision to comprehend larger effectivity, lower vitality, and optimize house (PPA).

And whereas the data that Samsung has developed a high-performance SoC using the Synopsys.ai suite is significant, there could also be one different, rather more very important dimension to this announcement: which implies that Samsung has lastly taped out a complicated smartphone software program processor on its cutting-edge 3nm GAAFET course of.

Although Samsung Foundry has been producing chips on its GAA-equipped SF3E (3 nm-class, ‘early’ node) course of for almost two years now, Samsung Electronics has not at all used this experience for its private system-on-chips for smartphones or totally different sophisticated items. Thus far, SF3E has been used primarily for cryptocurrency mining chips, presumably due to the inevitable early teething and yield factors that embrace being the commerce’s first enterprise GAAFET course of.

For now, Samsung just isn’t disclosing what explicit course of node is getting used for the SoC; the official Samsung/Synposys announcement solely notes that it’s for a GAA course of node. Along with their first-generation 3nm-class SF3E, Samsung Foundry has a considerably additional refined SF3 manufacturing experience that gives fairly a couple of enhancements over SF3E, and is due to be used for mass manufacturing throughout the coming quarters. Given the timing of the announcement, the inexpensive wager is that they’re using SF3.

As for Samsung’s tooling partnership with Synopsys, the latter’s devices are being credited for delivering some essential effectivity enhancements to the chip’s design. Particularly, the two firms are crediting these devices for enhancing the chip’s peak clockspeed by 300MHz whereas chopping down on dynamic vitality utilization by 10%. To carry out that, Samsung Electronics’ SoC builders used design partitioning optimization, multi-source clock tree synthesis (MSCTS), and good wire optimization to chop again signal interference, along with a easier hierarchical technique. And thru the usage of Synopsys Fusion Compiler, they did all this whereas with the power to skip weeks of ‘handbook’ design work, based mostly on the joint press launch.

“Our longstanding collaboration has delivered trendy SoC designs,” said Kijoon Hong, vice chairman of SLSI at Samsung Electronics. “It’s a distinctive milestone to effectively receive one of the best effectivity, vitality and house on primarily probably the most superior cell CPU cores and SoC designs in collaboration with Synopsys. Not solely have we demonstrated that AI-driven choices will assist us receive PPA targets for even primarily probably the most superior GAA course of utilized sciences, nevertheless by our partnership we now have established an ultra-high-productivity design system that is continually delivering spectacular outcomes.”