2nm Unveil in June, Second-Gen SF3 3nm Hits Manufacturing This 12 months

As part of Samsung’s Q1 earnings announcement, the company has outlined a couple of of its foundry unit’s key plans for the rest of the 12 months. The company has confirmed that it stays on monitor to meeting its objective of starting mass manufacturing of chips on its SF3 (3 nm-class, 2nd Expertise) know-how inside the second half of the 12 months. Within the meantime in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) course of know-how, which may provide a combination of effectivity and effectivity enhancements. Lastly, the company the company is preparing a variation of its 4 nm-class know-how for integration into stacked 3D designs.

SF2 To Be Unveiled In June

Samsung plans to disclose key particulars about its SF2 fabrication know-how on the VLSI Symposium 2024 on June 19. This is able to be the agency’s second major course of node based totally upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Bettering over its predecessor, SF2 will attribute a ‘distinctive epitaxial and integration course of,’ which may give the strategy node larger effectivity and reduce leakage than standard FinFET-based nodes (though Samsung isn’t disclosing the exact node they’re evaluating it to).

Samsung says that SF2 will enhance effectivity of slim transistors by 29% for N-type and 46% for P-type, and broad transistors by 11% and 23% respectively. Moreover, it reduces transistor worldwide variation by 26% compared with FinFET know-how, and cuts product leakage by roughly 50%. This course of moreover models the stage for future developments in know-how via enhanced design know-how co-optimization (DTCO) collaboration with its prospects.

One issue that Samsung has not talked about in context of SF2 is backside vitality provide, so not lower than for the second, there is not a indication that Samsung will most likely be adopting this next-gen vitality routing attribute for SF2.

Samsung says that the design infrastructure for SF2 – the PDK, EDA devices, and licensed IP – will most likely be finalized inside the second quarter of 2024. As quickly as this happens, Samsung’s chip enchancment companions can have the flexibility to begin designing merchandise for this manufacturing node. Within the meantime, Samsung is already working with Arm to co-optimize Arm’s Cortex cores for the SF2 course of.

SF3: On Monitor for 2H 2024

As the first fab to introduce a GAAFET-based node, Samsung has been on the chopping fringe of chip constructing. On the an identical time, nonetheless, that has moreover meant that they’re the first fab to come back throughout and resolve the inevitable teething factors that embrace such a severe transistor design change. Consequently, whereas Samsung’s first-generation SF3E course of know-how has been in manufacturing for slightly lower than two years now, the one publicly-disclosed chips made on the strategy thus far have been comparatively small cryptocurrency mining chips – exactly the type of pipecleaner elements that do correctly on a model new course of node.

Nonetheless with which have in hand, Samsung is on the point of maneuver on to creating bigger and better chips with GAAFETs. As part of their earnings bulletins, the company has confirmed that their updated SF3 node, which was launched ultimate 12 months, stays on schedule to enter manufacturing inside the second half of 2024.

A further mature product from the get-go, SF3 is being prepared to be used for setting up larger processors, along with datacenter merchandise. As compared with its direct predecessor, SF4, SF3 ensures a 22% effectivity enhance on the an identical vitality and transistor rely, or a 34% lower vitality on the an identical frequency and complexity, along with a 21% logic area low cost. Usually, Samsung pins quite a few hopes on this know-how, as a result of it is this period of their 3nm-class know-how that is poised to compete in the direction of TSMC’s N3B and N3E nodes.

SF4: Ready for 3D Stacking

Lastly, Samsung can be preparing a variant of their remaining FinFET know-how node, SF4, for use in 3D chiplet stacking. As transistor density enhancements have continued to gradual, 3D chip stacking has emerged as a choice to carry boosting complete chip effectivity, significantly with modern, multi-tile processor designs.

Particulars on this node are restricted, nevertheless it may seem that Samsung is making some changes to account/optimize for using SF4-fabbed chiplets in a 3D-stacked design, the place chips need to have the flexibility to speak every up and down. In step with the company’s Q1 financial report, Samsung expects to complete their preparatory work on the chip-stacking SF4 variant in the middle of the current quarter (Q2).

Sources: Samsung, Samsung